
module MemController(if_mc_en, if_mc_addr, mc_if_data, mem_mc_rw, mem_mc_en, mem_mc_addr, mem_mc_data, mem_mc_en1h, mem_mc_en1l, mem_mc_en2h, mem_mc_en2l, mc_ram_addr, mc_ram_rw, mc_ram_en1h, mc_ram_data1h, mc_ram_en1l, mc_ram_data1l, mc_ram_en2h, mc_ram_data2h, mc_ram_en2l, mc_ram_data2l);

	// Fetch
	input			if_mc_en;
	input	[31:0]	if_mc_addr;
	output	[31:0]	mc_if_data;
	
	// Memory
	input			mem_mc_rw;
	input			mem_mc_en;
	input	[31:0]	mem_mc_addr;
	inout	[31:0]	mem_mc_data;
	input			mem_mc_en1h;
	input			mem_mc_en1l;
	input			mem_mc_en2h;
	input			mem_mc_en2l;
	
	// Ram
	output	[31:0]	mc_ram_addr;
	output			mc_ram_rw;
	output			mc_ram_en1h;
	inout	[7:0]	mc_ram_data1h;
	output			mc_ram_en1l;
	inout	[7:0]	mc_ram_data1l;
	output			mc_ram_en2h;
	inout	[7:0]	mc_ram_data2h;
	output			mc_ram_en2l;
	inout	[7:0]	mc_ram_data2l;

	...
	
endmodule



